// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  blk_sch_cfg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  Yau Shek Fan
// Version       :  1.0
// Date          :  2017/7/10
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Yau Shek Fan 2018/03/19 11:46:48 Create file
// ******************************************************************************

#ifndef __BLK_SCH_CFG_REG_OFFSET_FIELD_H__
#define __BLK_SCH_CFG_REG_OFFSET_FIELD_H__

#define BLK_SCH_CFG_INITIALIZED_LEN    1
#define BLK_SCH_CFG_INITIALIZED_OFFSET 1
#define BLK_SCH_CFG_INITIAL_SEQ_LEN    1
#define BLK_SCH_CFG_INITIAL_SEQ_OFFSET 0

#define BLK_SCH_CFG_AIC_SECURE_MODE_LEN    1
#define BLK_SCH_CFG_AIC_SECURE_MODE_OFFSET 1
#define BLK_SCH_CFG_INT_BYPASS_LEN         1
#define BLK_SCH_CFG_INT_BYPASS_OFFSET      0

#define BLK_SCH_CFG_FAST_PATH_MODE_LEN         1
#define BLK_SCH_CFG_FAST_PATH_MODE_OFFSET      2
#define BLK_SCH_CFG_FUNCTIONAL_RESET_LEN       1
#define BLK_SCH_CFG_FUNCTIONAL_RESET_OFFSET    1
#define BLK_SCH_CFG_FORCE_CACHE_INVALID_LEN    1
#define BLK_SCH_CFG_FORCE_CACHE_INVALID_OFFSET 0

#define BLK_SCH_CFG_BO_UPDATE_MODE_LEN      1
#define BLK_SCH_CFG_BO_UPDATE_MODE_OFFSET   3
#define BLK_SCH_CFG_STALL_EN_LEN            1
#define BLK_SCH_CFG_STALL_EN_OFFSET         1
#define BLK_SCH_CFG_STALL_ALLOCATION_LEN    1
#define BLK_SCH_CFG_STALL_ALLOCATION_OFFSET 0

#define BLK_SCH_CFG_SP_LEVEL_LEN    3
#define BLK_SCH_CFG_SP_LEVEL_OFFSET 0

#define BLK_SCH_CFG_BO_TIMEOUT_CNT_LEN    16
#define BLK_SCH_CFG_BO_TIMEOUT_CNT_OFFSET 0

#define BLK_SCH_CFG_BO_CODE_LEN    8
#define BLK_SCH_CFG_BO_CODE_OFFSET 0

#define BLK_SCH_CFG_TSC_TIMEOUT_CNT_LO_LEN    32
#define BLK_SCH_CFG_TSC_TIMEOUT_CNT_LO_OFFSET 0

#define BLK_SCH_CFG_TSC_TIMEOUT_CNT_HI_LEN    8
#define BLK_SCH_CFG_TSC_TIMEOUT_CNT_HI_OFFSET 0

#define BLK_SCH_CFG_BSC_DEBUG_PAUSE_LEN    1
#define BLK_SCH_CFG_BSC_DEBUG_PAUSE_OFFSET 0

#define BLK_SCH_CFG_RESET_OVERHEAD_LEN    8
#define BLK_SCH_CFG_RESET_OVERHEAD_OFFSET 0

#define BLK_SCH_CFG_SECURE_CODE_LEN    32
#define BLK_SCH_CFG_SECURE_CODE_OFFSET 0

#define BLK_SCH_CFG_PING_PONG_MODE_LEN    1
#define BLK_SCH_CFG_PING_PONG_MODE_OFFSET 0

#define BLK_SCH_CFG_ERROR_CLEAR_LEN    1
#define BLK_SCH_CFG_ERROR_CLEAR_OFFSET 0

#define BLK_SCH_CFG_CORE_DISABLE_LEN    1
#define BLK_SCH_CFG_CORE_DISABLE_OFFSET 3
#define BLK_SCH_CFG_BO_EXCEPTION_LEN    1
#define BLK_SCH_CFG_BO_EXCEPTION_OFFSET 1
#define BLK_SCH_CFG_BO_DONE_LEN         1
#define BLK_SCH_CFG_BO_DONE_OFFSET      0

#define BLK_SCH_CFG_TASK_DONE_LEN    32
#define BLK_SCH_CFG_TASK_DONE_OFFSET 0

#define BLK_SCH_CFG_TASK_DEBUG_LEN    32
#define BLK_SCH_CFG_TASK_DEBUG_OFFSET 0

#define BLK_SCH_CFG_TASK_EXCEPTION_LEN    32
#define BLK_SCH_CFG_TASK_EXCEPTION_OFFSET 0

#define BLK_SCH_CFG_CORE_DISABLE_INT_MSK_LEN    1
#define BLK_SCH_CFG_CORE_DISABLE_INT_MSK_OFFSET 3
#define BLK_SCH_CFG_BO_EXCEPTION_INT_MSK_LEN    1
#define BLK_SCH_CFG_BO_EXCEPTION_INT_MSK_OFFSET 1
#define BLK_SCH_CFG_BO_DONE_INT_MSK_LEN         1
#define BLK_SCH_CFG_BO_DONE_INT_MSK_OFFSET      0

#define BLK_SCH_CFG_TASK_DONE_INT_MSK_LEN    32
#define BLK_SCH_CFG_TASK_DONE_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_TASK_DEBUG_INT_MSK_LEN    32
#define BLK_SCH_CFG_TASK_DEBUG_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_TASK_EXCEPTION_INT_MSK_LEN    32
#define BLK_SCH_CFG_TASK_EXCEPTION_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_CORE_DISABLE_INT_SET_LEN    1
#define BLK_SCH_CFG_CORE_DISABLE_INT_SET_OFFSET 3
#define BLK_SCH_CFG_BO_EXCEPTION_INT_SET_LEN    1
#define BLK_SCH_CFG_BO_EXCEPTION_INT_SET_OFFSET 1
#define BLK_SCH_CFG_BO_DONE_INT_SET_LEN         1
#define BLK_SCH_CFG_BO_DONE_INT_SET_OFFSET      0

#define BLK_SCH_CFG_TASK_DONE_INT_SET_LEN    32
#define BLK_SCH_CFG_TASK_DONE_INT_SET_OFFSET 0

#define BLK_SCH_CFG_TASK_DEBUG_INT_SET_LEN    32
#define BLK_SCH_CFG_TASK_DEBUG_INT_SET_OFFSET 0

#define BLK_SCH_CFG_TASK_EXCEPTION_INT_SET_LEN    32
#define BLK_SCH_CFG_TASK_EXCEPTION_INT_SET_OFFSET 0

#define BLK_SCH_CFG_CORE_DONE_LEN    32
#define BLK_SCH_CFG_CORE_DONE_OFFSET 0

#define BLK_SCH_CFG_CORE_DEBUG_LEN    32
#define BLK_SCH_CFG_CORE_DEBUG_OFFSET 0

#define BLK_SCH_CFG_CORE_EXCEPTION_LEN    32
#define BLK_SCH_CFG_CORE_EXCEPTION_OFFSET 0

#define BLK_SCH_CFG_CORE_DONE_INT_MSK_LEN    32
#define BLK_SCH_CFG_CORE_DONE_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_CORE_DEBUG_INT_MSK_LEN    32
#define BLK_SCH_CFG_CORE_DEBUG_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_CORE_EXCEPTION_INT_MSK_LEN    32
#define BLK_SCH_CFG_CORE_EXCEPTION_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_CORE_DONE_INT_SET_LEN    32
#define BLK_SCH_CFG_CORE_DONE_INT_SET_OFFSET 0

#define BLK_SCH_CFG_CORE_DEBUG_INT_SET_LEN    32
#define BLK_SCH_CFG_CORE_DEBUG_INT_SET_OFFSET 0

#define BLK_SCH_CFG_CORE_EXCEPTION_INT_SET_LEN    32
#define BLK_SCH_CFG_CORE_EXCEPTION_INT_SET_OFFSET 0

#define BLK_SCH_CFG_TASK_DFX_LEN    32
#define BLK_SCH_CFG_TASK_DFX_OFFSET 0

#define BLK_SCH_CFG_TASK_DFX_INT_SET_LEN    32
#define BLK_SCH_CFG_TASK_DFX_INT_SET_OFFSET 0

#define BLK_SCH_CFG_TASK_DFX_INT_MSK_LEN    32
#define BLK_SCH_CFG_TASK_DFX_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_TASK_PAUSED_LEN    32
#define BLK_SCH_CFG_TASK_PAUSED_OFFSET 0

#define BLK_SCH_CFG_TASK_PAUSED_INT_SET_LEN    32
#define BLK_SCH_CFG_TASK_PAUSED_INT_SET_OFFSET 0

#define BLK_SCH_CFG_TASK_PAUSED_INT_MSK_LEN    32
#define BLK_SCH_CFG_TASK_PAUSED_INT_MSK_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_0_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_0_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_1_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_1_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_2_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_2_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_3_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_3_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_4_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_4_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_5_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_5_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_6_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_6_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_7_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_7_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_8_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_8_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_9_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_9_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_10_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_10_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_11_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_11_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_12_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_12_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_13_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_13_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_14_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_14_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_15_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_15_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_16_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_16_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_17_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_17_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_18_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_18_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_19_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_19_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_20_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_20_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_21_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_21_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_22_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_22_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_23_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_23_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_24_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_24_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_25_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_25_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_26_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_26_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_27_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_27_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_28_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_28_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_29_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_29_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_30_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_30_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_31_LEN    6
#define BLK_SCH_CFG_CORE_CUR_TASK_31_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_0_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_0_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_1_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_1_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_2_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_2_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_3_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_3_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_4_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_4_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_5_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_5_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_6_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_6_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_7_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_7_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_8_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_8_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_9_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_9_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_10_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_10_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_11_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_11_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_12_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_12_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_13_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_13_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_14_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_14_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_15_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_15_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_16_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_16_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_17_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_17_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_18_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_18_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_19_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_19_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_20_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_20_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_21_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_21_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_22_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_22_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_23_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_23_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_24_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_24_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_25_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_25_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_26_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_26_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_27_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_27_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_28_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_28_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_29_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_29_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_30_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_30_OFFSET 0

#define BLK_SCH_CFG_CORE_CUR_TASK_BM_31_LEN    32
#define BLK_SCH_CFG_CORE_CUR_TASK_BM_31_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_0_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_0_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_1_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_1_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_2_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_2_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_3_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_3_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_4_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_4_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_5_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_5_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_6_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_6_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_7_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_7_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_8_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_8_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_9_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_9_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_10_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_10_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_11_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_11_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_12_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_12_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_13_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_13_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_14_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_14_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_15_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_15_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_16_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_16_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_17_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_17_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_18_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_18_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_19_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_19_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_20_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_20_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_21_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_21_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_22_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_22_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_23_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_23_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_24_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_24_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_25_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_25_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_26_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_26_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_27_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_27_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_28_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_28_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_29_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_29_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_30_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_30_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_31_LEN    32
#define BLK_SCH_CFG_PHY_CORE_ADDR_LO_31_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_0_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_0_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_1_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_1_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_2_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_2_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_3_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_3_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_4_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_4_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_5_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_5_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_6_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_6_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_7_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_7_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_8_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_8_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_9_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_9_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_10_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_10_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_11_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_11_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_12_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_12_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_13_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_13_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_14_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_14_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_15_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_15_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_16_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_16_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_17_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_17_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_18_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_18_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_19_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_19_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_20_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_20_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_21_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_21_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_22_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_22_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_23_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_23_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_24_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_24_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_25_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_25_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_26_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_26_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_27_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_27_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_28_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_28_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_29_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_29_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_30_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_30_OFFSET 0

#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_31_LEN    16
#define BLK_SCH_CFG_PHY_CORE_ADDR_HI_31_OFFSET 0

#define BLK_SCH_CFG_CORE_ERROR_0_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_0_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_0_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_0_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_0_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_0_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_0_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_0_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_0_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_0_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_1_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_1_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_1_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_1_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_1_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_1_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_1_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_1_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_1_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_1_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_2_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_2_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_2_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_2_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_2_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_2_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_2_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_2_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_2_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_2_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_3_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_3_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_3_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_3_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_3_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_3_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_3_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_3_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_3_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_3_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_4_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_4_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_4_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_4_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_4_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_4_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_4_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_4_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_4_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_4_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_5_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_5_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_5_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_5_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_5_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_5_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_5_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_5_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_5_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_5_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_6_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_6_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_6_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_6_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_6_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_6_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_6_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_6_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_6_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_6_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_7_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_7_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_7_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_7_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_7_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_7_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_7_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_7_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_7_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_7_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_8_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_8_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_8_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_8_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_8_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_8_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_8_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_8_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_8_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_8_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_9_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_9_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_9_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_9_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_9_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_9_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_9_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_9_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_9_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_9_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_10_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_10_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_10_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_10_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_10_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_10_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_10_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_10_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_10_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_10_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_11_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_11_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_11_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_11_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_11_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_11_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_11_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_11_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_11_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_11_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_12_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_12_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_12_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_12_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_12_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_12_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_12_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_12_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_12_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_12_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_13_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_13_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_13_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_13_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_13_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_13_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_13_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_13_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_13_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_13_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_14_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_14_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_14_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_14_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_14_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_14_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_14_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_14_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_14_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_14_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_15_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_15_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_15_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_15_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_15_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_15_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_15_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_15_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_15_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_15_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_16_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_16_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_16_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_16_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_16_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_16_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_16_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_16_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_16_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_16_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_17_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_17_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_17_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_17_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_17_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_17_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_17_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_17_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_17_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_17_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_18_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_18_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_18_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_18_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_18_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_18_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_18_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_18_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_18_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_18_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_19_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_19_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_19_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_19_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_19_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_19_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_19_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_19_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_19_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_19_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_20_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_20_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_20_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_20_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_20_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_20_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_20_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_20_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_20_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_20_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_21_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_21_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_21_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_21_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_21_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_21_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_21_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_21_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_21_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_21_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_22_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_22_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_22_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_22_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_22_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_22_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_22_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_22_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_22_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_22_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_23_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_23_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_23_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_23_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_23_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_23_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_23_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_23_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_23_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_23_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_24_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_24_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_24_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_24_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_24_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_24_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_24_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_24_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_24_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_24_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_25_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_25_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_25_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_25_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_25_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_25_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_25_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_25_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_25_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_25_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_26_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_26_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_26_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_26_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_26_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_26_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_26_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_26_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_26_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_26_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_27_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_27_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_27_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_27_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_27_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_27_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_27_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_27_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_27_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_27_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_28_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_28_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_28_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_28_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_28_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_28_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_28_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_28_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_28_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_28_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_29_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_29_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_29_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_29_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_29_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_29_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_29_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_29_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_29_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_29_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_30_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_30_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_30_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_30_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_30_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_30_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_30_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_30_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_30_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_30_OFFSET     0

#define BLK_SCH_CFG_CORE_ERROR_31_LEN         1
#define BLK_SCH_CFG_CORE_ERROR_31_OFFSET      20
#define BLK_SCH_CFG_CORE_ERROR_CODE_31_LEN    4
#define BLK_SCH_CFG_CORE_ERROR_CODE_31_OFFSET 16
#define BLK_SCH_CFG_GROUP_NUM_31_LEN          2
#define BLK_SCH_CFG_GROUP_NUM_31_OFFSET       8
#define BLK_SCH_CFG_VIR_CORE_EN_31_LEN        1
#define BLK_SCH_CFG_VIR_CORE_EN_31_OFFSET     6
#define BLK_SCH_CFG_PHY_CORE_ID_31_LEN        6
#define BLK_SCH_CFG_PHY_CORE_ID_31_OFFSET     0

#define BLK_SCH_CFG_VIR_CORE_VALID_LEN    32
#define BLK_SCH_CFG_VIR_CORE_VALID_OFFSET 0

#endif // __BLK_SCH_CFG_REG_OFFSET_FIELD_H__
